1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly to a semiconductor device having a planar element structure, and its manufacture.
2. Description of the Prior Art
In nearly all practical cases, wirings are formed on only one side of a semiconductor substrate of a semiconductor device such as a metal-insulator-semiconductor field-effect transistor (MISFET) formed on the surface of the substrate. Formation of wirings on the front side of the substrate is a natural idea and is easy to execute as well. Namely, it needs only to deposit an insulating film on the front surface of the substrate, open through holes in the insulating film, and form wirings over the holes.
On the other hand, wirings are made intricate and high density along with the increase in the density of the semiconductor devices resulting from miniaturization of the elements. This situation can be handled by providing a plurality of wiring layers, which can be achieved by repeating successively the deposition of the insulating layer and the formation of the wirings. In this way, it is possible to lay intricate wirings, and suppress the parasitic capacitance between the wirings by reducing the wiring density per layer and elevate the performance of the semiconductor device as well.
However, a wiring has generally to be connected eventually to some kind of element on the substrate. Now, as the number of wirings layers increase, extra areas are required to connect the upper layer wirings to the elements on the substrate. This is because when a wiring in an upper layer is connected to an element on the substrate, it becomes necessary for a wiring on a lower layer to detour around the connection section, and this tendency becomes more conspicuous as the number of the wiring layers increases. This fact obstructs the increase in the level of integration of the wirings, and eventually that of the semiconductor device as a whole.
Under these circumstances, formation of wirings on the rear surface of the semiconductor device is proposed in Japanese Laid-Open Patent Publication No. 62-139356. In general, in a vertical bipolar transistor consisting of an emitter, base and collector, the collector layer is formed at a position with the largest depth of the substrate. For this reason, it is general to realize the connection of a wiring on the front surface of the substrate to the collector by extending the collector layer sideways so as to avoid the transistor region. However, it results in a problem that the level of integration cannot be improved because of an extra area required for extending the collector sideways.
In Japanese Laid-Open Patent Publication No. 62-139356, it is shown that the extra area can be saved by forming a wiring to be connected with the collector on the rear surface of the substrate. Note, however, that this effect is peculiar to the bipolar transistor, and that a similar effect cannot be expected in particular for the MISFET having a planar element structure.
Another problem of a semiconductor device using miniaturized MISFETs is that of the parasitic capacitances arising from the proximity of the gate electrode to the wirings connected to the source and drain regions. Namely, as a result of reduction, along with the miniaturization, in the distances between the gate electrode and the wirings connected to the source and drain regions the parasitic capacitances are increased and the element performance is deteriorated. In particular, the parasitic capacitance generated between the gate electrode and the wiring of the drain region in the FET spoils substantially the performance of the miniaturized FET owing to the so-called Miller effect (a phenomenon in which the effect of a capacitance found between the input terminal and the output terminal is amplified).
As in the above, in a semiconductor device such as a MISFET having the gate electrode, source region and drain region as a planar element structure, there is a problem that when a multilayer interconnection is employed, the number of arrangeable wirings does not increase in proportion to the number of the wiring layers. The reason for this is that it is necessary to secure extra areas for connecting wirings on upper layers to elements on the substrate, and that wirings on intermediate layers have to detour around the extra areas. Besides, in the MISFET there is a problem that the parasitic capacitances between the gate electrode and the wirings of the source and drain regions are increased along with the miniaturization of the FET. This problem arises from the fact that the distances between the gate electrode and the wirings of the source and drain regions are diminished.